Numerically controlled oscillators (NCOs) are used to generate digital waveforms at a specific frequency for a variety of uses such as in communications (e.g., cell phones or wireless internet). One example of a prior art numerically controlled oscillator, is illustrated in FIG. 1, as NCO 100. A NCO may also be referred to as a direct digital synthesizer (DDS). However, this is somewhat of a misnomer because, typically a DDS is the combination of an NCO and a digital-to-analog converter. NCO 100 includes phase accumulator 110 and phase to amplitude converter 120. NCO 100 receives input signal 101 and generates output signal 102, which is provided to digital-to-analog converter (DAC) 130.
The NCO of FIG. 1 relies on a different technique than that of an analog system to generate a wave at a desired frequency. Whereas a typical analog system may make use of an oscillator locked to a reference frequency, NCO 100 relies on the clock frequency of the associated digital device, such as DAC 130, to digitally create a sinusoidal waveform. The digital representation of the sinusoidal wave is output from NCO 100 as signal 102.
In generating the digital representation of the sinusoidal wave, input signal 101 is received at NCO 100. Signal 101 is a ratio of a desired frequency of the output divided by the clock frequency of the system. This ratio provides the phase step for each clock cycle of the system (e.g., a ratio of 0.1 is indicative of a one-tenth cycle change along the wave at each clock cycle of the system). Signal 101 passes through phase accumulator 110. Phase accumulator 110 is a component that determines the phase of a signal at a given instant of time. Phase accumulator 110 operates based on the theory that, for a constant frequency, the derivative of phase is a line whose slope is the normalized frequency. In this example, phase accumulator 110 adds f0 cycles of phase to signal 101 once per clock period (where f0 is the ratio of the desired frequency to the clock frequency of accumulator 110). Phase accumulator 110 performs this adding in order to determine which portion of the sinusoidal wave corresponds to signal 101 at each clock cycle.
Phase accumulator 110 includes summer 111 and delay block 112. At each clock cycle, summer 111 receives from delay block 112 the value of a previous output from accumulator 110 and adds that value to the current value. In the example where the desired frequency is constant, summer 111 adds a constant fractional value in relation to the clock frequency. For example, if the desired frequency for the sinusoidal wave is 1/10 of the clock rate, then summer 111 adds a constant 0.1 (where 0.1 is a decimal representation in cycles of the desired frequency) to the value from delay block 112 for each iteration.
The output of phase accumulator 110 is the phase angle, or θn. By way of example, if NCO 100 starts at zero, the first output of accumulator 110 would be zero and the value of delay block 112 would also be zero. The next output cycle from accumulator 110 would be  0.1. This output value would also be provided to delay block 112, whose value would be incremented to 0.1. At this cycle there is no additive effect at summer 111 as the value of delay block 112 was originally zero. At the third cycle through accumulator 110, the value output from the accumulator is 0.2. (i.e. 0.1 frequency input plus the 0.1 value held in delay block 112) This output value of 0.2 is then stored in delay block 112, and added to the next output from accumulator 110 through summer 111. This additive effect acts to ramp up the value of accumulator 110.
Output θn of accumulator 110 is input to phase to amplitude converter 120 (“PAC”). PAC 120 takes the value of the phase received from phase accumulator 110 and converts that value to an amplitude on the corresponding sinusoidal wave. Typically, PAC 120 uses an index of values that associates a radian phase with an amplitude. This amplitude value is then output from PAC 120 as output signal 102.
Output signal 102 is provided to digital to analog converter 130. Digital to analog converter 130 converts the digital amplitude waveforms to analog signals forming a sinusoidal wave. One existing limitation to current NCOs is that the computation of phase to amplitude at PAC 120 is limited to the clock rate of the device upon which NCO 100 is disposed. Further, the output frequency cannot be more than one half the clock rate due to the Nyquist limit. In other words the largest value that can be input as input signal 101 in this example is 0.5. Thus, if NCO 100 has a clock rate of 500 MHz, the highest output frequency is 250 MHz. This phenomenon results from the fact that if a system the input signal 101 exceeds 0.5 by some value ε, phase accumulator 110 produces an output that is indistinguishable from that of a system whose input signal 101 is 1-ε. These clock rate limitations have become an increasing problem as the speed of digital-to-analog converters (as well as other circuitry using the output from NCOs) has increased significantly. However, the speeds of numerically controlled oscillators, such as NCO 100 cannot typically keep up with the speeds of the digital to analog converters (and other devices) as the accumulation and look-ups cannot be performed fast enough. Further, given these limitations NCO 100 cannot typically be used in a field programmable gate array (FPGA). Specifically, current FPGAs have an absolute maximum clock rate far below that of state of the art DACs. Currently, NCOs disposed on an FPGA cannot take advantage of these higher speed DACs.